Electrostatic discharge (ESD) damage is a well known phenomenon and can occur during the fabrication of semiconductor devices such as metal-oxide semiconductor (MOS) structures. In structures of this nature, ESD damage can result in gate insulating layer breakdown, large shifts in threshold voltage and large leakage currents between the gate and source electrodes or gate and drain electrodes.
ESD damage is a more pronounced problem during the fabrication of thin film transistor (TFT) switch arrays for use in liquid crystal displays or in flat panel detectors for radiation imaging. This is due to the fact that the TFT switches are formed on an insulating substrate (typically glass) and thus, the source and drain electrodes may charge to a very high voltage. Also, because peripheral circuits to which the TFT switch array is to be connected are generally not formed on the same substrate as the TFT switch array, the gate and source lines must extend from the TFT switch array sufficiently to allow the peripheral circuits to be connected to the TFT switch array via wire bonding pads. Any static charge picked up by the gate and source lines is transferred to the gate and source electrodes of the TFT switches as well as to the intersecting nodes of the gate and source lines where the static charge is held. If the static charge reaches a high enough level, the dielectric gate insulating layer between the gate and source electrodes may breakdown. Even if this breakdown can be avoided, the voltage differential between the gate and source electrodes or gate and drain electrodes caused by this held static charge may cause the threshold voltage of the TFT switches to shift in either a positive or negative direction.
Recently, a large amount of attention has been given to the problems resulting from ESD damage especially in active matrix liquid crystal displays and flat panel detectors for radiation imaging. It is now believed that ESD damage is also caused by equipment related problems during the fabrication, handling and testing of these types of devices. The trends to use higher throughput equipment with higher speed substrate handling as well as to downscale during the fabrication process to reduce metal line width and reduce parasitic capacitance in the TFT switches decrease ESD immunity.
One common ESD damage protection circuit used with TFT switch arrays makes use of closed shorting bars surrounding the TFT switch array to link all of the source lines and the gate lines of the TFT switch array together. The shorting bar associated with the gate lines is formed at the time the gate lines are formed while the shorting bar associated with the source lines is formed at the time the source lines are formed. The two shorting bars are electrically connected through vias formed in the TFT switch array structure. Because the shorting bars connect the gate and source electrodes of all of the TFT switches in the array, the gate and source electrodes remain at the same potential throughout the fabrication process. This prevents any voltage differentials from occurring across the gate and source electrodes and therefore, inhibits ESD damage at these electrodes.
Once the TFT switch array has been completely fabricated, the shorting bars are removed by cutting off part of the glass substrate where the shorting bars located. This cutting process is done before the individual TFT switches are tested and before the gate and source lines are connected to peripheral circuits.
Although the above ESD damage protection circuit is widely used, once the shorting bars have been removed, to ESD damage protection remains. This poses problems since ESD damage often occurs during testing of the TFT switches and during bonding of the gate and source lines to peripheral equipment. This is in view of the fact that at this stage, the TFT switch array is handled by individuals and contacted with electronic measuring equipment.
Another ESD damage protection network for TFT switch arrays is disclosed in U.S. Pat. No. 4,803,536. This ESD damage protection network makes use of a strip of N.sup.+ amorphous silicon resistive material film extending to all of the bonding pads. The value of the resistive material film is at least an order of magnitude greater than the impedance of external driver circuits connected to the bonding pads. By manipulating the resistance of the resistive material film, static charges disperse to all of the gate and source lines with an RC constant. Although individual TFT switches can be tested without removing the resistive material film, the resistive material film crosses over all of the gate and source lines. This causes crosstalk and electronic noise which in certain applications, such as x-ray imaging where signal currents are small, are serious problems.
U.S. Pat. No. 5,313,319 discloses yet another ESD protection circuit for a TFT switch array. This protection circuit includes static protection capacitors formed on the substrate of the TFT switch array between the gate and source lines. The thickness of the static protection capacitors are chosen to ensure that they breakdown due to static charges before ESD damage to the TFT switches occurs. Unfortunately, the static protection capacitors increase stray capacitance in the TFT switch array thereby increasing electronic noise making the TFT switch array unsuitable for many applications.
Japanese Patent Nos. JPA2-61618, JPA62-198826 and JPA1-303416 and U.S. Pat. No. 5,371,351 disclose an ESD protection circuit for a TFT switch array which makes use of photodiodes formed of an a-Si film. The photodiodes connect the gate lines with the source lines to minimize any potential voltage difference between them. When the photodiodes are illuminated, the resistance of the protection circuit decreases dramatically creating short circuits between the gate and source lines. When testing individual TFT switches, or when operating the TFT switch array in normal conditions, no incident light is permitted to impinge on the photodiodes. This keeps the resistance of the protection circuit very high to minimize crosstalk and leakage currents.
U.S. Pat. No. 5,220,443 discloses an ESD protection circuit for a TFT switch array. The protection circuit includes a common electrode interconnecting the gate and source lines. Non-linear resistive elements having a resistance that decreases with an increase in voltage are connected between the gate and source lines. The non-linear resistive elements are realized using two back to back thin film diodes. Because the resistive elements provide a large resistance between the gate and source lines, individual TFT switches can be tested without cutting the glass substrate. Even after cutting the glass substrate, some of the non-linear resistive elements remain to improve the immunity of the TFT switch array to ESD damage. However, the immunity of the TFT switch array to ESD damage after cutting is significantly less than before cutting.
The prior art ESD protection circuits referred to above all have some common drawbacks. Firstly, none of the ESD protection circuits protect the TFT switch array from the first manufacturing stage (usually gate line formation) to the last manufacturing stage (usually wire bonding). During the manufacture of TFT switch arrays for liquid crystal displays, it has been found that ESD damage may occur during the process of spin coating or stripping photoresist, during the cleaning process using DI water, and during plasma etching. These processes are often performed prior to the completion of the TFT switch array structure. Isolating the gate lines before finishing source line metallization as suggested in the prior art may result in the build up of electrostatic charge on the gate lines. Electrostatic charges on the gate lines may become buried under the dielectric film forming the gate insulating layer and incubate until later stages in the manufacturing process. During these later stages, the buried electrostatic charges may move along the gate lines and concentrate at a few points or boundary lines causing a breakdown in the dielectric gate insulating layer.
In addition, in some instances since the gate and source lines are interconnected by protection elements, a failure in the connection between a gate or source line and a protection element will result in the gate or source line being isolated from the common electrode.
In the case of U.S. Pat. No. 5,220,443, although some ESD damage protection circuitry remains on the substrate during the wire bonding process, the impedance between an arbitrary gate line and a source line may become too large to discharge electrostatic charge quickly enough to avoid ESD damage. Accordingly, better protection against ESD damage is desired.
It is therefore an object of the present invention to provide a reliable method of protecting a semiconductor switch array from ESD damage and a semiconductor switch array incorporating electrostatic discharge protection which obviates or mitigates at least one of the above-described disadvantages.